Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability

ABSTRACT

A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

TECHNICAL FIELD

[0001] This invention relates to methods for testing semiconductorcircuitry for operability, and to constructions and methods of formingtesting apparatus for operability testing of semiconductor circuitry.

BACKGROUND OF THE INVENTION

[0002] This invention grew out of the needs and problems associated withmulti-chip modules, although the invention will be applicable in othertechnologies associated with circuit testing and testing apparatusconstruction. Considerable advancement has occurred in the last fiftyyears in electronic development and packaging. Integrated circuitdensity has and continues to increase at a significant rate. However bythe 1980's, the increase in density in integrated circuitry was notbeing matched with a corresponding increase in density of theinterconnecting circuitry external of circuitry formed within a chip.Many new packaging technologies have emerged, including that of“multichip module” technology.

[0003] In many cases, multichip modules can be fabricated faster andmore cheaply than by designing new substrate integrated circuitry.Multichip module technology is advantageous because of the densityincrease. With increased density comes equivalent improvements in signalpropagation speed and overall device weight unmatched by other means.Current multichip module construction typically consists of a printedcircuit board substrate to which a series of integrated circuitcomponents are directly adhered.

[0004] Many semiconductor chip fabrication methods package individualdies in a protecting, encapsulating material. Electrical connections aremade by wire bond or tape to external pin leads adapted for plugginginto sockets on a circuit board. However, with multichip moduleconstructions, non-encapsulated chips or dies are secured to asubstrate, typically using adhesive, and have outwardly exposed bondingpads. Wire or other bonding is then made between the bonding pads on theunpackaged chips and electrical leads on the substrate.

[0005] Much of the integrity/reliability testing of multichip moduledies is not conducted until the chip is substantially complete in itsconstruction. Considerable reliability testing must be conducted priorto shipment. In one aspect, existing technology provides temporary wirebonds to the wire pads on the die for performing the various requiredtests. However, this is a low-volume operation and further requires thetest bond wire to ultimately be removed. This can lead to irreparabledamage, thus effectively destroying the chip.

[0006] Another prior art test technique uses a series of pointed probeswhich are aligned to physically engage the various bonding pads on achip. One probe is provided for engaging each bonding pad for providinga desired electrical connection. One drawback with such testing is thatthe pins undesirably on occasion penetrate completely through thebonding pads, or scratch the bonding pads possibly leading to chip ruin.

[0007] It would be desirable to overcome these and other drawbacksassociated with testing semiconductor circuitry for operability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic representation of a fragment of asubstrate processed in accordance with the invention.

[0010]FIG. 2 is a view of the FIG. 1 substrate fragment at a processingstep subsequent to that shown by FIG. 1.

[0011]FIG. 3 is a perspective view of the FIG. 2 substrate fragment.

[0012]FIG. 4 is a view of the FIG. 1 substrate fragment at a processingstep subsequent to that shown by FIG. 2.

[0013]FIG. 5 is a view of the FIG. 1 substrate fragment at a processingstep subsequent to that shown by FIG. 4.

[0014]FIG. 6 is a perspective view of the FIG. 5 substrate fragment.

[0015]FIG. 7 is a view of the FIG. 1 substrate fragment at a processingstep subsequent to that shown by FIG. 5.

[0016]FIG. 8 is a view of the FIG. 1 substrate fragment at a processingstep subsequent to that shown by FIG. 7.

[0017]FIG. 9 is a perspective view of a substrate fragment processed inaccordance with the invention.

[0018]FIG. 10 is a view of a substrate fragment processed in accordancewith the invention.

[0019]FIG. 11 is a view of the FIG. 10 substrate fragment at aprocessing step subsequent to that shown by FIG. 10.

[0020]FIG. 12 is a view of the FIG. 10 substrate fragment at aprocessing step subsequent to that shown by FIG. 11.

[0021]FIG. 13 is a view of the FIG. 10 substrate fragment at aprocessing step subsequent to that shown by FIG. 12.

[0022]FIG. 14 is a view of the FIG. 13 substrate in a testing method inaccordance with the invention.

[0023]FIG. 15 is a view of a substrate fragment processed in accordancewith the invention.

[0024]FIG. 16 is a view of the FIG. 15 substrate fragment at aprocessing step subsequent to that shown by FIG. 15.

[0025]FIG. 17 is a view of the FIG. 15 substrate fragment at aprocessing step subsequent to that shown by FIG. 16.

[0026]FIG. 18 is a view of a substrate fragment processed ia accordancewith the invention.

[0027]FIG. 19 is a view of the FIG. 18 substrate fragment at aprocessing step subsequent to that shown by FIG. 18.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0029] In accordance with one aspect of the invention, a method ofengaging electrically conductive test pads on a semiconductor substratehaving integrated circuitry for operability testing thereof comprisesthe following sequential steps:

[0030] providing an engagement probe having an outer surface comprisinga grouping of a plurality of electrically conductive projecting apexespositioned in proximity to one another to engage a single test pad on asemiconductor substrate;

[0031] engaging the grouping of apexes with the single test pad on thesemiconductor substrate; and

[0032] sending an electric signal between the grouping of apexes andtest pad to evaluate operability of integrated circuitry on thesemiconductor substrate.

[0033] In accordance with another aspect of the invention, a method offorming a testing apparatus for engaging electrically conductive testpads on a semiconductor substrate having integrated circuitry foroperability testing thereof, comprises the following steps:

[0034] providing a locally substantially planar outer surface of a firstmaterial on a semiconductor substrate;

[0035] providing a layer of second material atop the substantiallyplanar outer surface of first material, the second material beingcapable of substantially masking the underlying first material;

[0036] patterning and etching the layer of second material toselectively outwardly expose the first material and define a grouping ofdiscrete first material masking blocks, the discrete first materialmasking blocks of the grouping having respective centers, the respectivecenters of the grouping being positioned in sufficient proximity to oneanother such that the centers of the grouping fall within confines of agiven single test pad which the apparatus is adapted to electricallyengage;

[0037] forming projecting apexes beneath the masking blocks at themasking block centers, the projecting apexes forming a group fallingwithin the confines of the given single test pad of which the apparatusis adapted to electrically engage;

[0038] removing the discrete first material masking blocks from thesubstrate after the exposing step; and

[0039] rendering the projecting apexes electrically conductive.

[0040] In accordance with yet another aspect of the invention, a testingapparatus for engaging electrically conductive test pads on asemiconductor substrate having integrated circuitry for operabilitytesting thereof comprises:

[0041] a test substrate; and

[0042] an engagement probe projecting from the test substrate to engagea single test pad on a semiconductor substrate having integratedcircuitry formed in the semiconductor substrate, the engagement probehaving an outer surface comprising a grouping of a plurality ofelectrically conductive projecting apexes positioned in sufficientproximity to one another to collectively engage the single test pad.

[0043] The discussion proceeds initially with description of methods forforming testing apparatus in accordance with the invention, and totesting apparatus construction. FIG. 1 illustrates a semiconductorsubstrate fragment 10 comprised of a bulk substrate 12, preferablyconstituting monocrystalline silicon. Substrate 12 includes a locallysubstantially planar outer surface 14 comprised of a first material. Ina preferred and the described embodiment, the first material constitutesthe material of bulk substrate 12, and is accordingly silicon. A layer16 of second material is provided atop the planar outer surface 14 ofthe first material. The composition of the second material is selectedto be capable of substantially masking the underlying first materialfrom oxidation when the semiconductor substrate is exposed to oxidizingconditions. Where the underlying first material comprises silicon, anexample and preferred second material is Si₃N₄. A typical thickness forlayer 16 would be from about 500 Angstroms to about 3000 Angstroms, withabout 1600 Angstroms being preferred.

[0044] Referring to FIGS. 2 and 3, second material layer 16 is patternedand etched to selectively outwardly expose the first material and definea grouping of discrete first material masking blocks 18, 20, 24 and 26.For purposes of the continuing discussion, the discrete first materialmasking blocks of the grouping have respective centers. The lead linesin FIG. 2 depicting each of blocks 18, 20, 22 and 24 point directly tothe lateral centers of the respective blocks. The respective centers ofthe grouping are positioned in sufficient proximity to one another suchthat the centers of the grouping will fall within the confines of agiven single test pad of which the apparatus is ultimately adapted toelectrically engage for test. Such will become more apparent from thecontinuing discussion.

[0045] As evidenced from FIG. 3, masking blocks 18, 20, 24 and 26 arepatterned in the form of lines or runners integrally joined with othermasking blocks/lines 28, 30, 32 and 34. The blocks/lines interconnect asshown to form first and second polygons 36, 38, with polygon 38 beingreceived entirely within polygon 36. Polygons 36 and 38 constitute agrouping 41 masking blocks the confines of which fall within the area ofa given single test pad of which the apparatus is ultimately adapted toelectrically engage for test.

[0046] Referring to FIG. 4, semiconductor substrate 10 is exposed tooxidizing conditions effective to oxidize the exposed outer surfaces offirst material. Such oxidizes a sufficient quantity of first material ina somewhat isotropic manner to form projecting apexes 40, 42, 44 and 46forming a group 43 which, as a result of the patterning of the preferrednitride layer 16, fall within the confines of the given single test padof which the apparatus is adapted to electrically engage. Such producesthe illustrated oxidized layer 48. Example oxidizing conditions toproduce such effect would be a wet oxidation, whereby oxygen is bubbledthrough H₂O while the substrate is exposed to 950° C.

[0047] Referring to FIG. 5, the oxidized first material 48 is strippedfrom the substrate. Example conditions for conducting such strippingwould include a hot H₃PO₄ wet etch. Thereafter, the discrete firstmaterial masking blocks 18, 20, 24, 26, 28, 30, 32 and 34 are removedfrom the substrate. An example condition for such stripping in a mannerwhich is selective to the underlying silicon apexes include a roomtemperature HF wet etch. Thus referring to FIG. 6, the steps ofpatterning and etching, exposing, and stripping form projecting apexesbeneath the masking blocks at the masking block centers, such projectingapexes being numbered 40, 42, 44, 46, 48, 50, 52 and 54, which are inthe form of multiple knife-edge lines. The knife-edge lines interconnectto form the illustrated polygons 36 and 38. The apexes andcorrespondingly knife-edged or pyramid formed polygons are sized andpositioned in sufficient proximity to fall within the confines of asingle test pad of which the apparatus is adapted to engage, as will bemore apparent from the continuing discussion.

[0048] Other ways could be utilized to form projecting apexes beneaththe masking blocks at the masking block centers. As but one example, awet or dry isotropic etch in place of the step depicted by FIG. 4 couldbe utilized. Such etching provides the effect of undercutting morematerial from directly beneath the masking blocks to create apexes, assuch areas or regions have greater time exposure to etching.

[0049] Referring again to FIG. 5, the oxidation step produces theillustrated apexes which project from a common plane 56. For purposes ofthe continuing discussion, the apexes can be considered as havingrespective tips 58 and bases 60, with bases 60 being coincident withcommon plane 56. For clarity, tip and base pairs are numbered only withreference to apexes 40 and 42. Bases 60 of adjacent projecting apexesare spaced from one another a distance sufficient to define apenetration stop plane 62 therebetween. Example spacings between apexeswould be 1 micron, while an example length of an individual stop planewould be from 3 to 10 microns. The function of penetration stop plane 62will be apparent from the continuing discussion. A tip 58 and base 60are provided at a projecting distance apart which is preferably designedto be about one-half the thickness of the test pad which the givenapparatus is adapted to engage.

[0050] Multiple oxidizing and stripping steps might be conducted tofurther sharpen and shrink the illustrated projecting apexes. Forexample and again with reference to FIG. 4, the illustrated constructionin such multiple steps would have layer 48 stripped leaving theillustrated masking blocks in place over the apexes. Then, the substratewould be subjected to another oxidation step which would further oxidizesubstrate first material 12, both downwardly and somewhat laterally inthe direction of the apexes, thus likely further sharpening the apexes.Then, the subsequently oxidized layer would be stripped from thesubstrate, thus resulting in deeper, sharper projections relative from aprojecting plane.

[0051] Referring to FIG. 7, apex group 43 is covered a nitride maskinglayer 64 and photopatterned. Referring to FIG. 8, silicon substrate 12is then etched into around the masked projecting apexes to form aprojection 64 outwardly of which grouping 43 of the projecting apexesproject. The masking material is then stripped.

[0052] More typically, multiple groups of projecting apexes andprojections would be provided, with each being adapted to engage a giventest pad on a particular chip. Further tiering for producingelectrically contact-engaging probes might also be conducted. FIG. 9illustrates such a construction having apex groups 43 a and 43 b formedatop respect projection 64 a and 64 b. A typical projecting distancefrom base 60 to tip 58 would be 0.5 microns, with a projection 64 being100 microns deep and 50 microns wide. Projections 64 a and 64 b in turnhave been formed atop elongated projections 66 a and 66 b, respectively.Such provides effective projecting platforms for engaging test pads aswill be apparent from the continuing discussion.

[0053] Next, the group of projecting apexes is rendered electricallyconductive, and connected with appropriate circuitry for providing atesting function. The discussion proceeds with reference to FIGS. 10-13for a first example method for doing so. Referring first to FIG. 10, asubstrate includes a pair of projections 64 c and 64 d having respectiveoutwardly projecting apex groups 43 c and 43 d. A layer of photoresistis deposited atop the substrate and patterned to provide photoresistblocks 68 as shown. Photoresist applies atop a substrate as a liquid,thus filling valleys in a substrate initially and not coating outermostprojections. Thus, the providing of photoresist to form blocks 68 isconducted to outwardly exposed projecting apex groups 43 c and 43 d, aswell as selected area 70 adjacent thereto. Photoresist blocks 68 coversselected remaining portions of the underlying substrate.

[0054] Referring to FIG. 11, electric current is applied to substrate 12to be effective to electroplate a layer of metal 72 onto outwardlyexposed projecting apex groupings 43 c and 43 d and adjacent area 70. Anexample material for layer 72 would be electroplated Ni, Al, Cu, etc. Anexample voltage and current where substrate 12 comprises silicon wouldbe 100V and 1 milliamp, respectively. Under such conditions, photoresistfunctions as an effective insulator such that metal deposition onlyoccurs on the electrically active surfaces in accordance withelectroplating techniques. Photoresist is then stripped from thesubstrate, leaving the FIG. 11 illustrated construction shown, which mayalso include a desired conductive runner 74 formed atop bulk substrate12 between projections 64 c and 64 d.

[0055] The preferred material for metal layer 72 is platinum, due to itsexcellent oxidation resistance. Unfortunately, it is difficult todirectly bond the typical copper or gold bonding wires to platinum.Accordingly, preferably an intervening aluminum bonding site isprovided. Referring to FIG. 12, an aluminum or aluminum alloy layer 76is blanket deposited atop the substrate. A layer of photoresist isdeposited and patterned to provide photoresist masking blocks 78. Thesubstrate would then be subjected to an etch of the aluminum material ina manner which was selective to the underlying platinum. Example etchingconditions would include a hot H₃PO₄ wet etch. Such leaves resultingelevated bonding blocks 80 of aluminum atop which a bonding wire 82 isconventionally bonded, as shown in FIG. 13.

[0056] The description proceeds with reference to FIG. 14 for utilizingsuch an apparatus for conducting electrical tests of a chip. FIG. 14illustrates the testing apparatus of FIG. 13 engaging a chip 85 which isbeing tested. Chip 85 comprises a substrate portion 86 and outwardlyexposed bonding pads 88. Protecting or encapsulating material 90 isprovided such that substrate 86 and circuitry associated therewith isprotected, with only bonding pads 88 being outwardly exposed. Bondingpads 88 have some thickness “A”.

[0057] Substrate 12 comprises a test substrate having engagement probes64 c and 64 d projecting therefrom. Such include respective electricallyconductive apexes groups 43 c and 43 d positioned in respectiveproximity to fall within the confines of and engage a single test pad 88on chip 85. Such apexes are engaged with the respective test pads, asshown.

[0058] The illustrated projecting apexes actually project in to half-wayinto the thickness of the bonding pads, a distance of approximatelyon-half “A”. The penetration stop surface 62 described with reference toFIG. 5 provides a stopping point for preventing the projecting pointsfrom extending further into bonding pads 88 than would be desired. Inconnecting the testing apparatus to chip 85, pressure would be monitoredduring engagement of the projecting tips relative to the pads 88. Atsome point during the projection, the force or back pressure against thetesting apparatus would geometrically increase as the penetration stopplane reaches the outer surface of the bonding pads 88, indicating thatfull penetration had occurred. At this point, the testing substrate andchip 85 would be effectively electrically engaged. An electric signalwould be sent between the respective grouping of apexes and respectivetest pads in conventional testing methods to evaluate operability ofintegrated circuitry formed within the semiconductor substrate 85.

[0059] Reference is made to FIGS. 15-17 for a description of analternate method of rendering projecting apexes electrically conductive.

[0060] Starting with FIG. 15, such are sectional views taken laterallythrough projection 64 a of FIG. 9. Referring to FIG. 16, an electricallyconductive nucleation layer 90 is blanket deposited atop the apexes andsubstrate. An example material would be elemental nickel deposited bysputter techniques. Photoresist is then applied and patterned as shownto produce photoresist blocks 92. Thus, the nucleation layer coatedprojecting apexes and selected area adjacent thereto is outwardlyexposed, while selected remaining nucleation layer coated portions ofthe substrate are coated by resist blocks 92. At this point, a currentis applied to nucleation layer 90 effective to electrodeposit a layer94, such as electroless deposited copper, to a thickness of 1 micron.Resist blocks 92 effectively insulate underlying nucleation layer 90from depositing copper atop the resist. An example voltage and currentwould be 5V and 1 milliamp, respectively.

[0061] Referring to FIG. 17, the resist is then stripped from thesubstrate. A dry plasma etch is then conducted which selectively removesthe exposed nickel nucleation layer 90 relative to copper layer 94, suchthat only copper over the illustrated nickel remains. Then if desiredand as shown, current is applied to the nucleation layer and coppermaterial in a manner and under conditions which electroless deposits a2000 Angstrom thick layer 96 of, for example, platinum, palladium oriridium. Wire bonding could then be conducted apart from apexes 43 autilizing an intervening block of aluminum.

[0062] Such technique is preferable to the previously describedelectroless deposition method in that lower voltage and current can beutilized in the electroless deposition method where a highly conductivenucleation layer is provided atop the substrate.

[0063] Another alternate and preferred technique for forming andrendering the projecting apexes conductive is shown with reference toFIGS. 18 and 19. Such is an alternate construction corresponding to thatconstruction shown by FIG. 10. FIG. 18 is the same as FIG. 10, but forthe addition of, a) an insulating layer 71, preferably SiO₂; and b) ametal nucleation layer 73, prior to the providing and patterning toproduce photoresist blocks 68. Such a process is preferable to thatshown by FIG. 10 to provide separation of the typical monocrystallinesilicon substrate 12 from direct contact with metal. FIG. 19 illustratesthe subsequent preferred electroless deposition of a metal layer 72using substrate nucleation layer 73 as a voltage source. With respect tothe embodiment shown by FIGS. 15-17, such also would preferably beprovided with an insulating layer prior to deposition of the nucleationlayer. An alternate and preferred material for layer 73 would bealuminum metal, with the subsequently electroless layer being comprisedessentially of platinum. Platinum could then be used as a masking layerto etch exposed aluminum after photoresist strip. An example etchchemistry for such etch would include a wet H₃PO₄ dip.

[0064] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of engaging electrically conductive test pads on asemiconductor substrate having integrated circuitry for operabilitytesting thereof, the method comprising the following sequential steps:providing an engagement probe having an outer surface comprising agrouping of a plurality of electrically conductive projecting apexespositioned in proximity to one another to engage a single test pad on asemiconductor substrate; engaging the grouping of apexes with the singletest pad on the semiconductor substrate; and sending an electric signalbetween the grouping of apexes and test pad to evaluate operability ofintegrated circuitry on the semiconductor substrate.
 2. The method ofengaging electrically conductive test pads of claim 1 wherein the stepof engaging comprises pressing the grouping of apexes against the singletest pad sufficiently to penetrate the apexes into the test pad.
 3. Themethod of engaging electrically conductive test pads of claim 1 whereinthe step of engaging comprises pressing the grouping of apexes againstthe single test pad sufficiently to penetrate the apexes into the testpad a distance of only about one-half the test pad thickness.
 4. Amethod of forming a testing apparatus for engaging electricallyconductive test pads on a semiconductor substrate having integratedcircuitry for operability testing thereof, the method comprising thefollowing steps: providing a locally substantially planar outer surfaceof a first material on a semiconductor substrate; providing a layer ofsecond material atop the substantially planar outer surface of firstmaterial, the second material being capable of substantially masking theunderlying first material; patterning and etching the layer of secondmaterial to selectively outwardly expose the first material and define agrouping of discrete first material masking blocks, the discrete firstmaterial masking blocks of the grouping having respective centers, therespective centers of the grouping being positioned in sufficientproximity to one another such that the centers of the grouping fallwithin confines of a given single test pad which the apparatus isadapted to electrically engage; forming projecting apexes beneath themasking blocks at the masking block centers, the projecting apexesforming a group falling within the confines of the given single test padof which the apparatus is adapted to electrically engage; removing thediscrete first material masking blocks from the substrate after theexposing step; and rendering the projecting apexes electricallyconductive.
 5. The method of forming a testing apparatus of claim 4wherein the second material is capable of substantially masking theunderlying first material from oxidation when the semiconductorsubstrate is exposed to oxidizing conditions, the step of forming theprojecting apexes comprises: exposing the semiconductor substrate tooxidizing conditions effective to oxidize the exposed outer surface offirst material and oxidize first material beneath the masking blocks toform the projecting apexes at the masking block centers, and furthercomprising stripping oxidized first material from the substrate.
 6. Themethod of forming a testing apparatus of claim 5 wherein the steps ofexposing and stripping comprise multiple exposing and stripping steps.7. The method of forming a testing apparatus of claim 5 wherein thefirst material predominately comprises silicon, and the second materialpredominately comprises a nitride.
 8. The method of forming a testingapparatus of claim 4 wherein the layer of second material is provided toa thickness of from about 500 Angstroms to about 3000 Angstroms.
 9. Themethod of forming a testing apparatus of claim 4 wherein the steps ofpatterning and etching and forming comprise forming multiple groupingsof discrete masking blocks and multiple groups of projecting apexes,each group being sized and configured for engaging a respective singletest pad.
 10. The method of forming a testing apparatus of claim 4wherein the steps of patterning and etching and forming produceprojecting apexes in the form of multiple knife-edge lines.
 11. Themethod of forming a testing apparatus of claim 4 wherein the steps ofpatterning and etching and forming produce projecting apexes in the formof multiple knife-edge lines, the multiple knife-edge linesinterconnecting to form at least one polygon.
 12. The method of forminga testing apparatus of claim 4 wherein the steps of patterning andetching and forming produce projecting apexes in the form of multipleknife-edge lines, the multiple knife-edge lines interconnecting to format least two polygons one of which is received entirely within theother.
 13. The method of forming a testing apparatus of claim 4 whereinthe apexes have a selected projecting distance, the projecting distancebeing about one-half the thickness of the test pad which the apparatusis adapted to engage.
 14. The method of forming a testing apparatus ofclaim 4 wherein the steps of patterning and etching and forming produceapexes which project from a common plane, the apexes having respectivetips and bases, the bases of adjacent projecting apexes being spacedfrom one another to define a penetration stop plane therebetween. 15.The method of forming a testing apparatus of claim 4 wherein the stepsof patterning and etching and forming produce apexes which project froma common plane, the apexes having respective tips and bases, the basesof adjacent projecting apexes being spaced from one another to define apenetration stop plane therebetween, the tips being a distance from thepenetration stop plane of about one-half the thickness of the test padwhich the apparatus is adapted to engage.
 16. The method of forming atesting apparatus of claim 4 further comprising masking the projectingapexes and etching into the substrate around the masked projectingapexes to form a projection outwardly of which the projecting apexesproject.
 17. The method of forming a testing apparatus of claim 4wherein the step of rendering comprises: providing and patterningphotoresist to outwardly expose the projecting apexes, selected areaadjacent thereto, and cover selected remaining portions of thesubstrate; applying a current to the substrate and electroplating ametal on the substrate onto the outwardly exposed projecting apexes andadjacent area; and stripping photoresist from the substrate.
 18. Themethod of forming a testing apparatus of claim 17 further comprising:depositing an electrically conductive nucleation layer atop the apexesand substrate prior to providing and patterning the photoresist; thestep of providing and patterning photoresist comprising outwardlyexposing the nucleation layer coated projecting apexes, selectednucleation layer coated area adjacent thereto, and cover selectedremaining nucleation layer coated portions of the substrate; the step ofapplying current to the substrate comprising applying current to thenucleation layer and electroplating the metal onto the outwardly exposednucleation layer coated projecting apexes and outwardly exposednucleation layer coated adjacent area; stripping photoresist from thesubstrate; and stripping nucleation layer material from the substrateselectively relative to the metal.
 19. The method of forming a testingapparatus of claim 17 further comprising: depositing an electricallyconductive nucleation layer atop the apexes and substrate prior toproviding and patterning the photoresist; the step of providing andpatterning photoresist comprising outwardly exposing the nucleationlayer coated projecting apexes, selected nucleation layer coated areaadjacent thereto, and cover selected remaining nucleation layer coatedportions of the substrate; the step of applying current to the substratecomprising applying current to the nucleation layer and electroplatingthe metal onto the outwardly exposed nucleation layer coated projectingapexes and outwardly exposed nucleation layer coated adjacent area;stripping photoresist from the substrate; stripping nucleation layermaterial from the substrate selectively relative to the metal; and afterstripping nucleation layer material from the substrate selectivelyrelative to the metal, applying another dose of current to thenucleation layer to electroplate another metal on top of the metal. 20.The method of forming a testing apparatus of claim 17 furthercomprising: prior to providing and patterning photoresist, providing aninsulating layer over the substrate and projecting apexes; afterproviding the insulating layer over the substrate but still prior toproviding and patterning photoresist, depositing an electricallyconductive nucleation layer atop the apexes; the step of providing andpatterning photoresist comprising outwardly exposing the insulatinglayer and nucleation layer coated projecting apexes, selected nucleationlayer exposed area adjacent thereto, and cover selected remainingnucleation layer coated portions of the substrate; the step of applyingcurrent to the substrate comprising applying current to the nucleationlayer and electroplating the metal onto the outwardly exposed nucleationlayer coated projecting apexes and outwardly exposed nucleation layercoated adjacent area; stripping photoresist from the substrate; andstripping nucleation layer material from the substrate selectivelyrelative to the metal.
 21. A testing apparatus for engaging electricallyconductive test pads on a semiconductor substrate having integratedcircuitry for operability testing thereof, the apparatus comprising: atest substrate; and an engagement probe projecting from the testsubstrate to engage a single test pad on a semiconductor substratehaving integrated circuitry formed in the semiconductor substrate, theengagement probe having an outer surface comprising a grouping of aplurality of electrically conductive projecting apexes positioned insufficient proximity to one another to collectively engage the singletest pad.
 22. The testing apparatus of claim 21 comprising a pluralityof such engagement probes.
 23. The testing apparatus of claim 21 whereinthe apexes are in the shape of multiple knife-edge lines.
 24. Thetesting apparatus of claim 21 wherein the apexes are in the shape ofmultiple knife-edge lines, the multiple knife-edge lines interconnectingto form at least one polygon.
 25. The testing apparatus of claim 21wherein the apexes are in the shape of multiple knife-edge lines, themultiple knife-edge lines interconnecting to form at least two polygonsone of which is received entirely within the other.
 26. The testingapparatus of claim 21 wherein the engagement probe is formed on aprojection from the substrate.
 27. The testing apparatus of claim 21wherein the apexes have a selected projecting distance, the projectingdistance being about one-half the thickness of the test pad which theapparatus is adapted to engage.
 28. The testing apparatus of claim 21wherein the apexes have a selected projecting distance, the projectingdistance being about one-half the thickness of the test pad which theapparatus is adapted to engage.
 29. The testing apparatus of claim 21wherein the apexes project from a common plane, the apexes havingrespective tips and bases, the bases of adjacent projecting apexes beingspaced from one another to define a penetration stop plane therebetween.30. The testing apparatus of claim 21 wherein the apexes project from acommon plane, the apexes having respective tips and bases, the bases ofadjacent projecting apexes being spaced from one another to define apenetration stop plane therebetween, the tips being a distance from thepenetration stop plane of about one-half the thickness of the test padwhich the apparatus is adapted to engage.